publications | Hong Chul Nam

2026

Energy-Based Operator Learning in Function Space

Hong Chul Nam^*, Jeonghwan Cheon^*, Jae Mo Shin, and 1 more author

In ICML 2026 AI for Science Workshop, 2026

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We propose Energy-Based Operators (EBOs), an architecture-agnostic framework for learning conditional distributions over functions on continuous domains. An EBO defines a scalar energy over target functions given an input function and induces a probability model through a Gaussian reference. The resulting score field is obtained as the gradient of the parametrized energy to perform function-space iterative energy minimization (EM). Our model shows strong performance in function generation, such as super-resolution and forecasting, over various 1D function classes (oscillations, damping, and Izhikevich) in comparison with prediction operators and denoising operators over various architecture backbones. Moreover, it achieves strong performance over PDEs, namely Navier-Stokes, Darcy flow and Burgers. Notably, our model successfully detects anomalous functions by automatically assigning high energy without any supervision. It enables seizure detection and volatility prediction after learning neural dynamics and market microstructure dynamics without pre-defined labels during training, highlighting its effectiveness for both learning dynamical systems and detecting functional anomalies arising in scientific simulations and modeling.
Operator Learning Using Weak Supervision from Walk-on-Spheres

Hrishikesh Viswanath^*, Hong Chul Nam^*, Xi Deng, and 3 more authors

arXiv preprint arXiv:2603.01193, 2026

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Training neural PDE solvers is often bottlenecked by expensive data generation or unstable physics-informed neural network (PINN) involving challenging optimization landscapes due to higher-order derivatives. To tackle this issue, we propose an alternative approach using Monte Carlo approaches to estimate the solution to the PDE as a stochastic process for weak supervision during training. Leveraging the Walk-on-Spheres method, we introduce a learning scheme called Walk-on-Spheres Neural Operator (WoS-NO) which uses weak supervision from WoS to train any given neural operator. We propose to amortize the cost of Monte Carlo walks across the distribution of PDE instances using stochastic representations from the WoS algorithm to generate cheap, noisy, estimates of the PDE solution during training. This is formulated into a data-free physics-informed objective where a neural operator is trained to regress against these weak supervisions, allowing the operator to learn a generalized solution map for an entire family of PDEs. This strategy does not require expensive pre-computed datasets, avoids computing higher-order derivatives for loss functions that are memory-intensive and unstable, and demonstrates zero-shot generalization to novel PDE parameters and domains. Experiments show that for the same number of training steps, our method exhibits up to 8.75x improvement in L2-error compared to standard physics-informed training schemes, up to 6.31x improvement in training speed, and reductions of up to 2.97x in GPU memory consumption.
Making Visible, Making Invisible: How an AI Scribe Reshapes Documentation Authority in Social Work

Eunki Joung, Hong Chul Nam, Geonhwi Hwang, and 2 more authors

In Trustworthy AI for Good (AI4GOOD) Workshop @ ICML 2026, 2026

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AI scribes have shown promise in reducing clinical documentation burden and are now extending into social work. Social work documentation, however, serves a distinct function: it mediates between individual clients and the welfare regime, determining eligibility and shaping whose needs are recognized. We designed and deployed Care Fish, an AI scribe technology probe for in-home older adult care in South Korea, with four social workers over two weeks. Participants reported that Care Fish improved documentation efficiency by surfacing information missed during client interviews, and they identified and corrected its errors during a re-entry step into their existing systems. The deployment also surfaced shifts in documentation practice. The recording and AI-generated citations acquired a form of authority that workers compared against their own observations, reinforcing an existing epistemological hierarchy in which institutional ways of knowing outrank both worker observation and client speech. The expectation of being recorded changed how both clients and workers spoke during case interviews. We discuss how these shifts bear on workers’ professional discretion and clients’ self-presentation and consider design directions that make the AI scribe’s own perspective visible to the workers who use it.

2025

Q-Guided Flow Q-Learning

Yejun Jang^*, Hong Chul Nam^*, Jeong Min Park, and 2 more authors

In CoRL 2025 Workshop RemembeRL, 2025

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Generative policies improve expressivity over Gaussian actors but often come with entangled training pipelines (e.g., joint actor-critic training, student-teacher distillation, or sequence-to-sequence planners). We introduce Q-Guided Flow Q-Learning (QFQL), an actor-critic framework where the actor is trained independently via conditional flow matching for behavior cloning, and the critic is trained separately via temporal-difference (TD) learning. At inference, actions are produced by integrating the flow field and adding a value-seeking correction proportional to the action-gradient of the critic, i.e., a guidance term β\nabla_a Q(s,a). This decoupled design simplifies optimization, reduces instability from joint updates, and enables controllable trade-offs between behavioral realism and value-seeking at test time. Empirically, QFQL achieves strong offline reinforcement learning (RL) performance and stable training across tasks without auxiliary student models or policy regularizers, making it a strong candidate for offline RL.
FuncFlow: A Generative Neural Operator Using Diffusion Model for Simulation Augmentation

Hong Chul Nam^*, Tae Il Oh^*, Chanwoo Park, and 1 more author

In International Compact Modeling Conference (ICMC), 2025

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Large-scale simulations of semiconductor devices are crucial for understanding their behavior, yet each iteration of these simulations can take hours or even days. The complexity of modern transistors intensifies this challenge, demanding even more simulations to capture their diverse characteristics accurately. On the other hand, with the emergence of foundation models and other learning-based methods in semiconductors, it becomes critical to develop a systematic methodology for curating abundant, high-quality device data. In response to these challenges, we propose FuncFlow, a generative neural operator for augmenting device simulations. FuncFlow learns the probability distribution of arbitrary device types and generates valid simulation results at the corresponding technology scale within seconds. We evaluate FuncFlow over capacitance-voltage (CV) curve generations at different technology scales and demonstrate that FuncFlow can successfully learn the distribution and generate physically valid CV curves at each scale, significantly reducing the simulation time.
Large Pre-trained Model Approach for Efficient Design Technology Co-Optimization

Premkumar Vincent, Yeongwoo Nam, Kyungmin Kim, and 9 more authors

In International Compact Modeling Conference (ICMC), 2025

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In this work, we present a novel approach using large pretrained models to generate compact models for semiconductor devices, accelerating design technology co-optimization (DTCO) in advanced technology nodes. Our pretrained models, initially trained on SPICE-generated planar MOSFET datasets, demonstrate strong adaptability to state-of-the-art logic technologies while maintaining high accuracy. By integrating these models with device-specific artificial neural networks (ANNs), we enable rapid compact model generation even with limited data. We validate our approach through DTCO analysis of vertically stacked nanosheet-based GAA-FETs, showing that it requires significantly fewer data points compared to conventional methods while enhancing both accuracy and simulation speed.

2024

FuncAnoDe: A Function Level Anomaly Detection in Device Simulation

Tae Il Oh^*, Hong Chul Nam^*, Chanwoo Park, and 1 more author

In 2024 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2024

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In semiconductor device simulations, the reliance on empirical compact models, such as the Berkeley Short-channel IGFET Model (BSIM) and neural compact models, introduces approximations that may significantly diverge from actual physical phenomena. Identifying and filtering out unphysical behaviors and erroneous simulation outcomes is a challenging task, traditionally requiring extensive expert involvement and incurring high costs. In response, we introduce FuncAnoDe, a novel neural operator for unsupervised functional anomaly detection in semiconductor simulation datasets. FuncAnoDe is the first to offer deep learning-based function-level anomaly detection without manual expert intervention. Its function-level encoder-decoder architecture enables applications across a diverse range of device parameters and simulations, ensuring scalability and high accuracy in identifying physically implausible parameter configurations. Our evaluations were conducted through complex capacitance-voltage (C-V) curve analysis, and FuncAnoDe demonstrated its effectiveness in anomaly detection by achieving a 100.00% accuracy without reliance on manual labeling. FuncAnoDe provides a methodological advancement that enhances the precision, reliability, and efficiency of semiconductor design and simulation workflows.
Solving Poisson Equations using Neural Walk-on-Spheres

Hong Chul Nam^*, Julius Berner^*, and Anima Anandkumar

In Proceedings of the 41st International Conference on Machine Learning, 21–27 Jul 2024

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We propose Neural Walk-on-Spheres (NWoS), a novel neural PDE solver for the efficient solution of high-dimensional Poisson equations. Leveraging stochastic representations and Walk-on-Spheres methods, we develop novel losses for neural networks based on the recursive solution of Poisson equations on spheres inside the domain. The resulting method is highly parallelizable and does not require spatial gradients for the loss. We provide a comprehensive comparison against competing methods based on PINNs, the Deep Ritz method, and (backward) stochastic differential equations. In several challenging, high-dimensional numerical examples, we demonstrate the superiority of NWoS in accuracy, speed, and computational costs. Compared to commonly used PINNs, our approach can reduce memory usage and errors by orders of magnitude. Furthermore, we apply NWoS to problems in PDE-constrained optimization and molecular dynamics to show its efficiency in practical applications.

2023

NPC-NIS: Navigating Semiconductor Process Corners with Neural Importance Sampling

Hong Chul Nam, and Chanwoo Park

In NeurIPS 2023 Workshop on Adaptive Experimental Design and Active Learning in the Real World, 2023

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Traditional corner case analysis in semiconductor circuit design typically involves the use of predetermined semiconductor process parameters, including Fast, Typical, and Slow corners for PMOS and NMOS devices, frequently yielding overly conservative designs due to the utilization of fixed, and potentially non-representative, process parameter values for circuit simulations. Identifying the worst cases of circuit FoMs within typical semiconductor process variation ranges presents a considerable challenge, especially given the complexities associated with accurately sampling rare semiconductor events. In response, we introduce NPC-NIS, a model specifically developed for estimating rare cases in semiconductor circuit analysis, leveraging a learnable importance sampling strategy. We model the distribution of process parameters that exhibit the worst FoMs within a realistic range. This adaptable framework dynamically identifies and addresses rare semiconductor cases within typical process variation ranges, enhancing our circuit design optimization capabilities under realistic conditions. Our empirical results validate the effectiveness of the Neural Importance Sampling (NIS) approach in identifying and mitigating rare semiconductor scenarios, thereby contributing to the development of more robust and reliable semiconductor circuit designs and connecting traditional semiconductor corner case analysis with realworld semiconductor applications.
FlowSim: An Invertible Generative Network for Efficient Statistical Analysis under Process Variations

Chanwoo Park^*, Hong Chul Nam^*, Jihun Park, and 1 more author

In 2023 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2023

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The analysis of statistical variation in circuits or devices, resulting from process, voltage, and temperature (PVT) variations, is a critical aspect of ensuring high yield and accurate high-sigma analysis in semiconductor fabrication. As the industry progresses toward nanometer technologies, process variation becomes a significant challenge, necessitating the development of effective statistical models. Traditional Monte Carlo simulations, however, struggle to scale with the increasing number of process variables, leading to an exponential growth in the required simulations. In response to this challenge, we introduce FlowSim, a novel approach that employs density estimation to accurately perform yield and high-sigma analysis with a significantly reduced number of simulations. This approach offers a unique solution to the scalability issues faced by conventional Monte Carlo simulations, providing over a 100x decrease in the number of required simulations while maintaining a prediction error below 5% across all statistical metrics of circuit performance.
Victima: Drastically Increasing Address Translation Reach by Leveraging Underutilized Cache Resources

Konstantinos Kanellopoulos, Hong Chul Nam, Nisa Bostanci, and 5 more authors

In Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, Toronto, ON, Canada, 2023

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Address translation is a performance bottleneck in data-intensive workloads due to large datasets and irregular access patterns that lead to frequent high-latency page table walks (PTWs). PTWs can be reduced by using (i) large hardware TLBs or (ii) large software-managed TLBs. Unfortunately, both solutions have significant drawbacks: increased access latency, power and area (for hardware TLBs), and costly memory accesses, the need for large contiguous memory blocks, and complex OS modifications (for software-managed TLBs). We present Victima, a new software-transparent mechanism that drastically increases the translation reach of the processor by leveraging the underutilized resources of the cache hierarchy. The key idea of Victima is to repurpose L2 cache blocks to store clusters of TLB entries, thereby providing an additional low-latency and high-capacity component that backs up the last-level TLB and thus reduces PTWs. Victima has two main components. First, a PTW cost predictor (PTW-CP) identifies costly-to-translate addresses based on the frequency and cost of the PTWs they lead to. Leveraging the PTW-CP, Victima uses the valuable cache space only for TLB entries that correspond to costly-to-translate pages, reducing the impact on cached application data. Second, a TLB-aware cache replacement policy prioritizes keeping TLB entries in the cache hierarchy by considering (i) the translation pressure (e.g., last-level TLB miss rate) and (ii) the reuse characteristics of the TLB entries. Our evaluation results show that in native (virtualized) execution environments Victima improves average end-to-end application performance by 7.4% (28.7%) over the baseline four-level radix-tree-based page table design and by 6.2% (20.1%) over a state-of-the-art software-managed TLB, across 11 diverse data-intensive workloads. Victima delivers similar performance as a system that employs an optimistic 128K-entry L2 TLB, while avoiding the associated area and power overheads. Victima (i) is effective in both native and virtualized environments, (ii) is completely transparent to application and system software, (iii) unlike large software-managed TLBs, does not require contiguous physical allocations, (iv) is compatible with modern large page mechanisms and (iv) incurs very small area and power overheads of and , respectively, on a modern high-end CPU. The source code of Victima is freely available at https://github.com/CMU-SAFARI/Victima.