publications

2025

1. FuncFlow: A Generative Neural Operator Using Diffusion Model for Simulation Augmentation

   Hong Chul Nam^*, Tae Il Oh^*, Chanwoo Park, and 1 more author

   In International Compact Modeling Conference (ICMC), 2025

   Abs

2. Large Pre-trained Model Approach for Efficient Design Technology Co-Optimization

   Premkumar Vincent, Yeongwoo Nam, Kyungmin Kim, and 9 more authors

   In International Compact Modeling Conference (ICMC), 2025

   Abs

2024

1. FuncAnoDe: A Function Level Anomaly Detection in Device Simulation

   Tae Il Oh^*, Hong Chul Nam^*, Chanwoo Park, and 1 more author

   In 2024 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2024

   Abs

   In semiconductor device simulations, the reliance on empirical compact models, such as the Berkeley Short-channel IGFET Model (BSIM) and neural compact models, introduces approximations that may significantly diverge from actual physical phenomena. Identifying and filtering out unphysical behaviors and erroneous simulation outcomes is a challenging task, traditionally requiring extensive expert involvement and incurring high costs. In response, we introduce FuncAnoDe, a novel neural operator for unsupervised functional anomaly detection in semiconductor simulation datasets. FuncAnoDe is the first to offer deep learning-based function-level anomaly detection without manual expert intervention. Its function-level encoder-decoder architecture enables applications across a diverse range of device parameters and simulations, ensuring scalability and high accuracy in identifying physically implausible parameter configurations. Our evaluations were conducted through complex capacitance-voltage (C-V) curve analysis, and FuncAnoDe demonstrated its effectiveness in anomaly detection by achieving a 100.00% accuracy without reliance on manual labeling. FuncAnoDe provides a methodological advancement that enhances the precision, reliability, and efficiency of semiconductor design and simulation workflows.

2. Solving Poisson Equations using Neural Walk-on-Spheres

   Hong Chul Nam^*, Julius Berner^*, and Anima Anandkumar

   In Proceedings of the 41st International Conference on Machine Learning, 21–27 jul 2024

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   We propose Neural Walk-on-Spheres (NWoS), a novel neural PDE solver for the efficient solution of high-dimensional Poisson equations. Leveraging stochastic representations and Walk-on-Spheres methods, we develop novel losses for neural networks based on the recursive solution of Poisson equations on spheres inside the domain. The resulting method is highly parallelizable and does not require spatial gradients for the loss. We provide a comprehensive comparison against competing methods based on PINNs, the Deep Ritz method, and (backward) stochastic differential equations. In several challenging, high-dimensional numerical examples, we demonstrate the superiority of NWoS in accuracy, speed, and computational costs. Compared to commonly used PINNs, our approach can reduce memory usage and errors by orders of magnitude. Furthermore, we apply NWoS to problems in PDE-constrained optimization and molecular dynamics to show its efficiency in practical applications.

2023

1. NPC-NIS: Navigating Semiconductor Process Corners with Neural Importance Sampling

   Hong Chul Nam, and Chanwoo Park

   In NeurIPS 2023 Workshop on Adaptive Experimental Design and Active Learning in the Real World, 21–27 jul 2023

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   Traditional corner case analysis in semiconductor circuit design typically involves the use of predetermined semiconductor process parameters, including Fast, Typical, and Slow corners for PMOS and NMOS devices, frequently yielding overly conservative designs due to the utilization of fixed, and potentially non-representative, process parameter values for circuit simulations. Identifying the worst cases of circuit FoMs within typical semiconductor process variation ranges presents a considerable challenge, especially given the complexities associated with accurately sampling rare semiconductor events. In response, we introduce NPC-NIS, a model specifically developed for estimating rare cases in semiconductor circuit analysis, leveraging a learnable importance sampling strategy. We model the distribution of process parameters that exhibit the worst FoMs within a realistic range. This adaptable framework dynamically identifies and addresses rare semiconductor cases within typical process variation ranges, enhancing our circuit design optimization capabilities under realistic conditions. Our empirical results validate the effectiveness of the Neural Importance Sampling (NIS) approach in identifying and mitigating rare semiconductor scenarios, thereby contributing to the development of more robust and reliable semiconductor circuit designs and connecting traditional semiconductor corner case analysis with realworld semiconductor applications.

2. FlowSim: An Invertible Generative Network for Efficient Statistical Analysis under Process Variations

   Chanwoo Park^*, Hong Chul Nam^*, Jihun Park, and 1 more author

   In 2023 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 21–27 jul 2023

   Abs

   The analysis of statistical variation in circuits or devices, resulting from process, voltage, and temperature (PVT) variations, is a critical aspect of ensuring high yield and accurate high-sigma analysis in semiconductor fabrication. As the industry progresses toward nanometer technologies, process variation becomes a significant challenge, necessitating the development of effective statistical models. Traditional Monte Carlo simulations, however, struggle to scale with the increasing number of process variables, leading to an exponential growth in the required simulations. In response to this challenge, we introduce FlowSim, a novel approach that employs density estimation to accurately perform yield and high-sigma analysis with a significantly reduced number of simulations. This approach offers a unique solution to the scalability issues faced by conventional Monte Carlo simulations, providing over a 100x decrease in the number of required simulations while maintaining a prediction error below 5% across all statistical metrics of circuit performance.

3. Victima: Drastically Increasing Address Translation Reach by Leveraging Underutilized Cache Resources

   Konstantinos Kanellopoulos, Hong Chul Nam, Nisa Bostanci, and 5 more authors

   In Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, Toronto, ON, Canada, 21–27 jul 2023

   Abs

   Address translation is a performance bottleneck in data-intensive workloads due to large datasets and irregular access patterns that lead to frequent high-latency page table walks (PTWs). PTWs can be reduced by using (i) large hardware TLBs or (ii) large software-managed TLBs. Unfortunately, both solutions have significant drawbacks: increased access latency, power and area (for hardware TLBs), and costly memory accesses, the need for large contiguous memory blocks, and complex OS modifications (for software-managed TLBs). We present Victima, a new software-transparent mechanism that drastically increases the translation reach of the processor by leveraging the underutilized resources of the cache hierarchy. The key idea of Victima is to repurpose L2 cache blocks to store clusters of TLB entries, thereby providing an additional low-latency and high-capacity component that backs up the last-level TLB and thus reduces PTWs. Victima has two main components. First, a PTW cost predictor (PTW-CP) identifies costly-to-translate addresses based on the frequency and cost of the PTWs they lead to. Leveraging the PTW-CP, Victima uses the valuable cache space only for TLB entries that correspond to costly-to-translate pages, reducing the impact on cached application data. Second, a TLB-aware cache replacement policy prioritizes keeping TLB entries in the cache hierarchy by considering (i) the translation pressure (e.g., last-level TLB miss rate) and (ii) the reuse characteristics of the TLB entries. Our evaluation results show that in native (virtualized) execution environments Victima improves average end-to-end application performance by 7.4% (28.7%) over the baseline four-level radix-tree-based page table design and by 6.2% (20.1%) over a state-of-the-art software-managed TLB, across 11 diverse data-intensive workloads. Victima delivers similar performance as a system that employs an optimistic 128K-entry L2 TLB, while avoiding the associated area and power overheads. Victima (i) is effective in both native and virtualized environments, (ii) is completely transparent to application and system software, (iii) unlike large software-managed TLBs, does not require contiguous physical allocations, (iv) is compatible with modern large page mechanisms and (iv) incurs very small area and power overheads of and , respectively, on a modern high-end CPU. The source code of Victima is freely available at https://github.com/CMU-SAFARI/Victima.